FreeCbb provides online parameterized generation of common hardware building blocks (Common Building Blocks, or CBBs). Select a module and configure its parameters to generate and download the corresponding Verilog RTL for your hardware design.
This Wiki provides module overviews, parameter descriptions, interface definitions, and usage examples to help you select, configure, and integrate modules.
Visit FreeCbb to browse IPs and start generating
Generation parameters determine the hardware structure of the generated module. Regenerate the module whenever you need a different configuration. Refer to each module's interface documentation for features that can be adjusted at runtime.
Visit the CBB Manual Directory for module features, parameters, interfaces, and usage examples.
Make sure the manual version matches the version of the module you select.
If a manual includes resource usage or performance data, also check the device, tool version, and parameter configuration used for those measurements.
This website has thoroughly verified the CBBs it provides, but does not guarantee that verification is exhaustive or that it covers all parameter combinations, use cases, and operating environments. Users should perform the necessary simulation, synthesis, timing analysis, and system verification for their specific applications.
Users bear sole responsibility for any consequences or losses arising from the use of the CBBs provided by this website and their generated code.
All code generated and delivered by this website is licensed under the MIT License.
If you find any bugs or have suggestions or other feedback, please contact us at [email protected].